AI compute that doesn’t move the data.
We build analog and digital in-memory compute for AI inference. The multiply-accumulate happens inside the memory array. The weights stay where they are.
The bottleneck isn’t arithmetic. It’s traffic.
Run an inference on a conventional accelerator and most of the energy never goes near the multiply. It goes into moving numbers — the same weights, pulled out of memory and pushed back, billions of times a second. Fetching a weight can cost more than the operation it feeds.
This is an architectural problem, not a process problem. A smaller node makes the transistors cheaper. It does not make the trip shorter.
In-memory compute deletes the trip.
Put the compute where the weights already live.
A memory array is a grid of storage cells. Drive a voltage along the rows and every cell passes a current set by what it has stored. The currents on a column add up on the wire. That sum is a dot product — the core operation of a neural network — and it took one step, in the analog domain, with nothing fetched and nothing written back.
We design the array, the cell, and every circuit around it.
Analog and digital. Both, because neither is enough on its own.
Analog in-memory compute
Weights are held as an analog quantity in the cell itself, and the array performs the matrix-vector multiply in a single step. That is where the efficiency comes from, and it is also where the hard problems are — cell variability, retention, read disturb, and getting the result back into the digital domain without spending the savings in the converter.
Digital in-memory compute
Not every layer tolerates analog error. We pair the analog array with SRAM-based digital in-memory macros for the stages that need bit-exact results, and for the parts of a network where accuracy matters more than power does.
Advanced device technology
Underneath both sits device work: TCAD simulation, compact model extraction, retention and variability characterisation, and integration into the process back end. In-memory compute fails at the device layer before it fails anywhere else, which is why our device people sit upstream of the design team rather than beside it.
We use AI to build the silicon, not only to run on it.
The argument that makes in-memory compute worth building applies to how we design it. The constraint in an analog design cycle is rarely insight. It is the number of simulations, corners and checks somebody has to grind through before the insight arrives. We put machine assistance on that grind and keep the judgement with engineers.
Design-space exploration.
Machine-guided sizing and corner selection across analog blocks, so the search runs wide before a designer narrows it by hand.
Pre-tape-out functional verification.
AI-assisted verification applied ahead of tape-out. On a prior production programme this approach cut development time by 30 to 50 percent.
Flow automation.
Script-driven RTL-to-GDSII pipelines in the Cadence environment — repeatable across projects, with the error-prone manual steps taken out.
Static sign-off.
Automated clock-domain, reset-domain and structural lint pipelines that catch metastability and timing hazards before synthesis rather than after it.
Every result is reviewed by a named engineer. We are deliberate about where machine assistance belongs in a flow whose output is a mask set.
Inference at the edge, where the power budget is the specification.
Always-on sensing
Devices that must listen or watch continuously on a battery, where the wake-up decision has to be made locally and cheaply.
Vision at the edge
Cameras and sensors that need to interpret a frame without sending it anywhere, for latency, cost or privacy reasons.
Industrial and automotive
Environments with a hard thermal ceiling and a long qualification cycle, where efficiency buys reliability rather than just battery life.
Constrained and high-reliability systems
Applications where every milliwatt is accounted for and parts are expected to behave predictably for years.
Two things that hold each other up.
DeltaChip develops in-memory compute technology for AI inference — the work set out under Technology.
We also run silicon design programmes for other companies: analog and mixed-signal design, physical design through to GDSII, device and process engineering, verification, and test. That business funds the compute work, keeps our engineers on current nodes with current tools, and means the research is done by people who deliver production silicon rather than papers.
Most companies attempting analog compute are a research team looking for a manufacturing partner. We came at it from the other end.
The bench
Analog and mixed-signal design · Device, process and memory · Physical design and layout · Digital and SoC · Test, package and production
This is not a software team that decided to build a chip. The core group has taken analog and mixed-signal silicon into production for three decades — data converters, references, memory, power management — alongside the process and device work underneath it.
Building something that has to think inside a power budget?
We take on IP development, joint development programmes, and design engagements from architecture through tape-out. Tell us what you are building and where the constraint is, and we will tell you whether we are the right people for it.
info@deltachip.co