In-memory compute, from the cell up.
The efficiency argument for in-memory compute is easy to make. The engineering is not. This page sets out what actually has to be solved and how we go at it.
A multiply is Ohm’s law. An accumulate is Kirchhoff’s.
Store a weight as the conductance of a cell. Apply an activation as a voltage on the row. The current through that cell is the product of the two — that is the multiply, and it is free, because it is just physics happening in a resistor.
Every cell on a column feeds the same wire, so the current arriving at the bottom is the sum of all those products. That is the dot product of the input vector with one column of the weight matrix.
The full matrix-vector multiply happens at once, in the time the array takes to settle. No instruction fetch. No register file. No data movement, because the operands were already in place.
Four problems decide whether this works.
Cell variability
Two nominally identical cells do not have identical conductance, and that difference lands directly on the weight as error. We attack it at the device level through characterisation and compact modelling, and at the circuit level through write-verify schemes and post-fabrication trim.
Retention and drift
An analog weight has to still be the same weight months later, across temperature. Retention is a device property, which is the reason our device work sits upstream of the design rather than alongside it.
The readout
What comes off the array is an analog current. Converting it back to digital can quietly consume the energy the array just saved. The converter is not a peripheral detail — it is part of the compute, and it is designed as part of the compute.
Mapping
A trained network has to be partitioned across arrays, quantised, and calibrated against how the silicon actually behaves rather than against an idealised model of it.
Where analog is the wrong answer.
Analog compute trades precision for energy. That is a good trade on many convolutional layers and a poor one elsewhere. Attention layers, final classification stages, and anything where a small error compounds through the network are better served by an SRAM-based digital in-memory macro — still no long data movement, but bit-exact results.
A useful part is usually both. We design for the split rather than defending one side of it.
The layers are not separable.
In-memory compute breaks when any one layer is treated as somebody else’s problem. A cell that behaves beautifully in isolation can be unusable once the write scheme and the sense amplifier are real. We work at all five layers with one team, which is unusual for a company this size and is the main reason we can attempt this at all.
We use AI to build the silicon, not only to run on it.
The argument for in-memory compute is that moving data is the expensive part. The argument for machine assistance in our own flow runs the same way. The expensive part of a silicon programme is rarely the insight. It is the volume of simulation, fitting, sizing and checking somebody has to work through before the insight arrives, and again afterwards to prove it holds. We put machine assistance on that volume and keep the judgement with engineers.
In the device and process layer
Surrogate models for multiphysics simulation.
Full three-dimensional TCAD is accurate and slow, which means it gets used to confirm decisions rather than to explore them. We train physics-informed neural networks on TCAD results — transport, thermal behaviour, defect dynamics — and use the trained surrogate to sweep a parameter space that would be impractical to simulate directly. The surrogate does not replace TCAD. It tells us which handful of points are worth simulating properly, which turns a sequential study into a parallel one.
Guided process and stack screening.
Bayesian optimisation across material and dimensional parameters, so a search that would otherwise run on intuition and a spreadsheet runs systematically instead. What comes back is a shortlist and a sense of how sharp each optimum is — and the sharpness matters more than the optimum, because a peak you cannot manufacture to is not a result.
Automated compact model extraction.
Fitting a device model by hand is slow, and it is where a great deal of quiet error enters a design kit. We automate the regression from measured and simulated data into Verilog-A models, including state-dependent behaviour and degradation terms, so what reaches the circuit designer carries the physics rather than a convenient approximation of it.
Generative variability modelling.
Measurements on single devices do not tell you how a large array behaves. We train generative models on cell-level variability data and use them to predict array-level distributions before anything is committed to silicon — which is the difference between discovering a yield problem in simulation and discovering it in a lot.
In the design and verification flow
Reinforcement-learning circuit sizing.
Sizing agents with simulation in the loop, applied to analog blocks where the trade-off surface is genuinely multidimensional — matching against area, bandwidth against power, settling against overshoot. The agent explores the surface. A designer decides which region of it is acceptable for this part.
Generated calibration maps.
Neural-network-generated calibration mapping that compensates known non-linearity and supply-drop behaviour, replacing a hand-tuned process that scales badly as arrays grow.
Pre-tape-out functional verification.
AI-assisted verification applied ahead of tape-out. On a prior production programme this approach cut development time by 30 to 50 percent.
Flow automation and static sign-off.
Script-driven RTL-to-GDSII pipelines in the Cadence environment, repeatable across projects. Automated clock-domain, reset-domain and structural lint analysis running continuously rather than as an end-of-cycle gate, so metastability and timing hazards surface before synthesis instead of after it.
None of this is autonomous. Every surrogate is checked against the simulation it was trained to approximate. Every fitted model is validated at the corners. Every result is reviewed by a named engineer. A tool that is right most of the time is a useful tool and not a sign-off, and we are deliberate about the difference in a flow whose output is a mask set.
| Stage | What the machine does | What the engineer decides |
|---|---|---|
| Process and stack exploration | Sweeps large parameter spaces through a trained surrogate in place of direct simulation | Which physics the surrogate has to reproduce, and which candidates earn a full simulation |
| Device modelling | Fits model parameters from measured and simulated data, including state-dependent and degradation terms | Whether the fit is physical, and where the model must not be trusted |
| Variability and yield | Predicts array-level distributions from cell-level data | What distribution is acceptable, and what the design has to tolerate without help |
| Circuit sizing | Searches the trade-off surface with simulation in the loop | Which trade-off is the right one for this part, and which corners are real |
| Verification | Generates and prioritises stimulus, flags anomalies for review | What constitutes coverage, and what is good enough to tape out |
| Physical implementation | Runs the flow end to end, identically, every time | Floorplan, constraints, and what closure actually means here |
| Static sign-off | Runs structural, clock-domain and reset-domain analysis continuously | Which waivers are legitimate and which are a deferred problem |
Working on a problem in this space?
We are interested in joint development, IP licensing conversations, and design engagements where the device layer matters.